EDN

Lattice FPGA design suite adds support for DDR interfaces

SAN FRANCISCO—Lattice Semiconductor Corp. Tuesday (Nov. 9) announced Version 8.0 of its ispLEVER FPGA design tool suite, which the company said includes enhancements for the design of high-speed ...
Design-Reuse

New Lattice FPGA Design Tool Suite Includes Advanced Support for High Performance DDR Interfaces

HILLSBORO, OR, Nov 10, 2009-- Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced Version 8.0 of its ispLEVER(R) FPGA design tool suite, which includes many enhancements for the design of ...
Design-Reuse

Core-assisted approach accelerates debug of FPGA DDR II interfaces

With IO rates of several hundred megahertz, FPGAs have become an excellent medium for implementation of high-speed memory controllers. Fast memory storage and retrieval often involve implementing DDR ...
EDN

Implementing custom DDR and DDR2 SDRAM external memory interfaces in FPGAs (part 1)

These design guidelines provide the best practices for DDR and DDR2 SDRAM custom memory interface implementation in Stratix III and Stratix IV FPGAs. Figure 1 shows the design flow that is required ...